# Copyright (c) 2022 The Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

from testlib import *

if config.bin_path:
    resource_path = config.bin_path
else:
    resource_path = joinpath(absdirpath(__file__), "..", "resources")

# The following lists the RISCV binaries. Those commented out presently result
# in a test failure. This is outlined in the following Jira issue:
# https://gem5.atlassian.net/browse/GEM5-496
rv64_binaries = (
    "rv64samt-ps-sysclone_d",
    "rv64samt-ps-sysfutex1_d",
    #    'rv64samt-ps-sysfutex2_d',
    "rv64samt-ps-sysfutex3_d",
    #    'rv64samt-ps-sysfutex_d',
    "rv64ua-ps-amoadd_d",
    "rv64ua-ps-amoadd_w",
    "rv64ua-ps-amoand_d",
    "rv64ua-ps-amoand_w",
    "rv64ua-ps-amomax_d",
    "rv64ua-ps-amomax_w",
    "rv64ua-ps-amomaxu_d",
    "rv64ua-ps-amomaxu_w",
    "rv64ua-ps-amomin_d",
    "rv64ua-ps-amomin_w",
    "rv64ua-ps-amominu_d",
    "rv64ua-ps-amominu_w",
    "rv64ua-ps-amoor_d",
    "rv64ua-ps-amoor_w",
    "rv64ua-ps-amoswap_d",
    "rv64ua-ps-amoswap_w",
    "rv64ua-ps-amoxor_d",
    "rv64ua-ps-amoxor_w",
    "rv64ua-ps-lrsc",
    "rv64uamt-ps-amoadd_d",
    "rv64uamt-ps-amoand_d",
    "rv64uamt-ps-amomax_d",
    "rv64uamt-ps-amomaxu_d",
    "rv64uamt-ps-amomin_d",
    "rv64uamt-ps-amominu_d",
    "rv64uamt-ps-amoor_d",
    "rv64uamt-ps-amoswap_d",
    "rv64uamt-ps-amoxor_d",
    "rv64uamt-ps-lrsc_d",
    "rv64uc-ps-rvc",
    "rv64ud-ps-fadd",
    "rv64ud-ps-fclass",
    "rv64ud-ps-fcmp",
    "rv64ud-ps-fcvt",
    "rv64ud-ps-fcvt_w",
    "rv64ud-ps-fdiv",
    "rv64ud-ps-fmadd",
    "rv64ud-ps-fmin",
    "rv64ud-ps-ldst",
    "rv64ud-ps-move",
    "rv64ud-ps-recoding",
    "rv64ud-ps-structural",
    "rv64uf-ps-fadd",
    "rv64uf-ps-fclass",
    "rv64uf-ps-fcmp",
    "rv64uf-ps-fcvt",
    "rv64uf-ps-fcvt_w",
    "rv64uf-ps-fdiv",
    "rv64uf-ps-fmadd",
    "rv64uf-ps-fmin",
    "rv64uf-ps-ldst",
    "rv64uf-ps-move",
    "rv64uf-ps-recoding",
    "rv64ui-ps-add",
    "rv64ui-ps-addi",
    "rv64ui-ps-addiw",
    "rv64ui-ps-addw",
    "rv64ui-ps-and",
    "rv64ui-ps-andi",
    "rv64ui-ps-auipc",
    "rv64ui-ps-beq",
    "rv64ui-ps-bge",
    "rv64ui-ps-bgeu",
    "rv64ui-ps-blt",
    "rv64ui-ps-bltu",
    "rv64ui-ps-bne",
    "rv64ui-ps-fence_i",
    "rv64ui-ps-jal",
    "rv64ui-ps-jalr",
    "rv64ui-ps-lb",
    "rv64ui-ps-lbu",
    "rv64ui-ps-ld",
    "rv64ui-ps-lh",
    "rv64ui-ps-lhu",
    "rv64ui-ps-lui",
    "rv64ui-ps-lw",
    "rv64ui-ps-lwu",
    "rv64ui-ps-or",
    "rv64ui-ps-ori",
    "rv64ui-ps-sb",
    "rv64ui-ps-sd",
    "rv64ui-ps-sh",
    "rv64ui-ps-simple",
    "rv64ui-ps-sll",
    "rv64ui-ps-slli",
    "rv64ui-ps-slliw",
    "rv64ui-ps-sllw",
    "rv64ui-ps-slt",
    "rv64ui-ps-slti",
    "rv64ui-ps-sltiu",
    "rv64ui-ps-sltu",
    "rv64ui-ps-sra",
    "rv64ui-ps-srai",
    "rv64ui-ps-sraiw",
    "rv64ui-ps-sraw",
    "rv64ui-ps-srl",
    "rv64ui-ps-srli",
    "rv64ui-ps-srliw",
    "rv64ui-ps-srlw",
    "rv64ui-ps-sub",
    "rv64ui-ps-subw",
    "rv64ui-ps-sw",
    "rv64ui-ps-xor",
    "rv64ui-ps-xori",
    "rv64um-ps-div",
    "rv64um-ps-divu",
    "rv64um-ps-divuw",
    "rv64um-ps-divw",
    "rv64um-ps-mul",
    "rv64um-ps-mulh",
    "rv64um-ps-mulhsu",
    "rv64um-ps-mulhu",
    "rv64um-ps-mulw",
    "rv64um-ps-rem",
    "rv64um-ps-remu",
    "rv64um-ps-remuw",
    "rv64um-ps-remw",
    "rv64uzfh-ps-fadd",
    "rv64uzfh-ps-fclass",
    "rv64uzfh-ps-fcmp",
    "rv64uzfh-ps-fcvt",
    "rv64uzfh-ps-fcvt_w",
    "rv64uzfh-ps-fdiv",
    "rv64uzfh-ps-fmadd",
    "rv64uzfh-ps-fmin",
    "rv64uzfh-ps-ldst",
    "rv64uzfh-ps-move",
    "rv64uzfh-ps-recoding",
    "rv64uzba-ps-add_uw",
    "rv64uzba-ps-sh1add",
    "rv64uzba-ps-sh1add_uw",
    "rv64uzba-ps-sh2add",
    "rv64uzba-ps-sh2add_uw",
    "rv64uzba-ps-sh3add",
    "rv64uzba-ps-sh3add_uw",
    "rv64uzba-ps-slli_uw",
    "rv64uzbb-ps-andn",
    "rv64uzbb-ps-clz",
    "rv64uzbb-ps-clzw",
    "rv64uzbb-ps-cpop",
    "rv64uzbb-ps-cpopw",
    "rv64uzbb-ps-ctz",
    "rv64uzbb-ps-ctzw",
    "rv64uzbb-ps-max",
    "rv64uzbb-ps-maxu",
    "rv64uzbb-ps-min",
    "rv64uzbb-ps-minu",
    "rv64uzbb-ps-orc_b",
    "rv64uzbb-ps-orn",
    "rv64uzbb-ps-rev8",
    "rv64uzbb-ps-rol",
    "rv64uzbb-ps-rolw",
    "rv64uzbb-ps-ror",
    "rv64uzbb-ps-rori",
    "rv64uzbb-ps-roriw",
    "rv64uzbb-ps-rorw",
    "rv64uzbb-ps-sext_b",
    "rv64uzbb-ps-sext_h",
    "rv64uzbb-ps-xnor",
    "rv64uzbb-ps-zext_h",
    "rv64uzbc-ps-clmul",
    "rv64uzbc-ps-clmulh",
    "rv64uzbc-ps-clmulr",
    "rv64uzbs-ps-bclr",
    "rv64uzbs-ps-bclri",
    "rv64uzbs-ps-bext",
    "rv64uzbs-ps-bexti",
    "rv64uzbs-ps-binv",
    "rv64uzbs-ps-binvi",
    "rv64uzbs-ps-bset",
    "rv64uzbs-ps-bseti",
)

rv32_binaries = (
    "rv32ua-ps-amoadd_w",
    "rv32ua-ps-amoand_w",
    "rv32ua-ps-amomaxu_w",
    "rv32ua-ps-amomax_w",
    "rv32ua-ps-amominu_w",
    "rv32ua-ps-amomin_w",
    "rv32ua-ps-amoor_w",
    "rv32ua-ps-amoswap_w",
    "rv32ua-ps-amoxor_w",
    "rv32ua-ps-lrsc",
    "rv32uamt-ps-amoadd_w",
    "rv32uamt-ps-amoand_w",
    "rv32uamt-ps-amomaxu_w",
    "rv32uamt-ps-amomax_w",
    "rv32uamt-ps-amominu_w",
    "rv32uamt-ps-amomin_w",
    "rv32uamt-ps-amoor_w",
    "rv32uamt-ps-amoswap_w",
    "rv32uamt-ps-amoxor_w",
    "rv32uamt-ps-lrsc_w",
    "rv32uc-ps-rvc",
    "rv32ud-ps-fadd",
    "rv32ud-ps-fclass",
    "rv32ud-ps-fcmp",
    "rv32ud-ps-fcvt",
    "rv32ud-ps-fcvt_w",
    "rv32ud-ps-fdiv",
    "rv32ud-ps-fmadd",
    "rv32ud-ps-fmin",
    "rv32ud-ps-ldst",
    "rv32ud-ps-recoding",
    "rv32uf-ps-fadd",
    "rv32uf-ps-fclass",
    "rv32uf-ps-fcmp",
    "rv32uf-ps-fcvt",
    "rv32uf-ps-fcvt_w",
    "rv32uf-ps-fdiv",
    "rv32uf-ps-fmadd",
    "rv32uf-ps-fmin",
    "rv32uf-ps-ldst",
    "rv32uf-ps-move",
    "rv32uf-ps-recoding",
    "rv32ui-ps-add",
    "rv32ui-ps-addi",
    "rv32ui-ps-and",
    "rv32ui-ps-andi",
    "rv32ui-ps-auipc",
    "rv32ui-ps-beq",
    "rv32ui-ps-bge",
    "rv32ui-ps-bgeu",
    "rv32ui-ps-blt",
    "rv32ui-ps-bltu",
    "rv32ui-ps-bne",
    "rv32ui-ps-fence_i",
    "rv32ui-ps-jal",
    "rv32ui-ps-jalr",
    "rv32ui-ps-lb",
    "rv32ui-ps-lbu",
    "rv32ui-ps-lh",
    "rv32ui-ps-lhu",
    "rv32ui-ps-lui",
    "rv32ui-ps-lw",
    "rv32ui-ps-or",
    "rv32ui-ps-ori",
    "rv32ui-ps-sb",
    "rv32ui-ps-sh",
    "rv32ui-ps-simple",
    "rv32ui-ps-sll",
    "rv32ui-ps-slli",
    "rv32ui-ps-slt",
    "rv32ui-ps-slti",
    "rv32ui-ps-sltiu",
    "rv32ui-ps-sltu",
    "rv32ui-ps-sra",
    "rv32ui-ps-srai",
    "rv32ui-ps-srl",
    "rv32ui-ps-srli",
    "rv32ui-ps-sub",
    "rv32ui-ps-sw",
    "rv32ui-ps-xor",
    "rv32ui-ps-xori",
    "rv32um-ps-div",
    "rv32um-ps-divu",
    "rv32um-ps-mul",
    "rv32um-ps-mulh",
    "rv32um-ps-mulhsu",
    "rv32um-ps-mulhu",
    "rv32um-ps-rem",
    "rv32um-ps-remu",
    "rv32uzfh-ps-fadd",
    "rv32uzfh-ps-fclass",
    "rv32uzfh-ps-fcmp",
    "rv32uzfh-ps-fcvt",
    "rv32uzfh-ps-fcvt_w",
    "rv32uzfh-ps-fdiv",
    "rv32uzfh-ps-fmadd",
    "rv32uzfh-ps-fmin",
    "rv32uzfh-ps-ldst",
    "rv32uzfh-ps-move",
    "rv32uzfh-ps-recoding",
    "rv32uzba-ps-sh1add",
    "rv32uzba-ps-sh2add",
    "rv32uzba-ps-sh3add",
    "rv32uzbb-ps-andn",
    "rv32uzbb-ps-clz",
    "rv32uzbb-ps-cpop",
    "rv32uzbb-ps-ctz",
    "rv32uzbb-ps-max",
    "rv32uzbb-ps-maxu",
    "rv32uzbb-ps-min",
    "rv32uzbb-ps-minu",
    "rv32uzbb-ps-orc_b",
    "rv32uzbb-ps-orn",
    "rv32uzbb-ps-rev8",
    "rv32uzbb-ps-rol",
    "rv32uzbb-ps-ror",
    "rv32uzbb-ps-rori",
    "rv32uzbb-ps-sext_b",
    "rv32uzbb-ps-sext_h",
    "rv32uzbb-ps-xnor",
    "rv32uzbb-ps-zext_h",
    "rv32uzbc-ps-clmul",
    "rv32uzbc-ps-clmulh",
    "rv32uzbc-ps-clmulr",
    "rv32uzbs-ps-bclr",
    "rv32uzbs-ps-bclri",
    "rv32uzbs-ps-bext",
    "rv32uzbs-ps-bexti",
    "rv32uzbs-ps-binv",
    "rv32uzbs-ps-binvi",
    "rv32uzbs-ps-bset",
    "rv32uzbs-ps-bseti",
)

cpu_types = ("atomic", "timing", "minor", "o3")

for cpu_type in cpu_types:
    for binary in rv64_binaries:
        gem5_verify_config(
            name=f"asm-riscv-{binary}-{cpu_type}",
            verifiers=(),
            config=joinpath(
                config.base_dir,
                "tests",
                "gem5",
                "asmtest",
                "configs",
                "riscv_asmtest.py",
            ),
            config_args=[
                binary,
                cpu_type,
                "--num-cores",
                "4",
                "--resource-directory",
                resource_path,
            ],
            valid_isas=(constants.all_compiled_tag,),
            valid_hosts=constants.supported_hosts,
        )
    for binary in rv32_binaries:
        gem5_verify_config(
            name=f"asm-riscv-{binary}-{cpu_type}",
            verifiers=(),
            config=joinpath(
                config.base_dir,
                "tests",
                "gem5",
                "asmtest",
                "configs",
                "riscv_asmtest.py",
            ),
            config_args=[
                binary,
                cpu_type,
                "--num-cores",
                "4",
                "--riscv-32bits",
                "--resource-directory",
                resource_path,
            ],
            valid_isas=(constants.all_compiled_tag,),
            valid_hosts=constants.supported_hosts,
        )
